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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com XR16M2551 high performance low voltage duart with 16-byte fifo and powersave feature may 2007 rev. 1.0.2 general description the XR16M2551 1 (m2551) is a high performance dual universal asynchronous receiver and transmitter (uart) with 16 byte tx and rx fifos. the device operates from 1.62 to 3.63 volts and is pin-to-pin compatible to the xr16l2551 and xr16v2551. the m2551 includes 2 additional capabilities over the xr16m2550: intel and motorola data bus selection and a ?powersave? mode to minimize the sleep current. it supports exar?s enhanced features of selectable fifo trigger level, aut omatic hardware (rts/cts) and software flow control, and a complete modem interface. an inte rnal loopback capability allows system diagno stics. independent programmable fractional baud rate generators are provided in each channel to select data rates up to 16 mbps at 3.3 volt and 4x sampling clock. the m2551 is available in 48-pin tqfp and 32-pin qfn packages. n ote : 1 covered by u.s. patent #5,649,122 applications ? portable appliances ? telecommunication network routers ? ethernet network routers ? cellular data devices ? factory automation and process controls features ? 1.62 to 3.63 volt operation ? pin-to-pin compatible to exar?s xr16v2551 and the xr16l2551 ? two independent uart channels register set is 16550 compatible data rate of up to 16 mbps at 3.3 v data rate of up to 12.5 mbps at 2.5 v data rate of up to 8 mbps at 1.8v fractional baud rate generator transmit and receive fifos of 16 bytes selectable tx and rx fifo trigger levels automatic hardware (rts/cts) flow control automatic software (xon/xoff) flow control wireless infrared (irda 1.0) encoder/decoder automatic sleep mode wi th wake-up interrupt full modem interface ? powersave feature reduces sleep current to 15 a ? device identification and revision ? crystal oscillator (up to 24mhz) or external clock (up to 64mhz) input ? 48-tqfp and 32-qfn packages f igure 1. XR16M2551 b lock d iagram xtal1 xtal2 crystal osc/buffer txa, rxa, dtra#, dsra#, rtsa#, dtsa#, cda#, ria#, op2a# intel or motorola data bus interface uart channel a 16 byte tx fifo 16 byte rx fifo brg ir endec tx & rx uart regs 1.62 to 3.63v vcc gnd txb, rxb, dtrb#, dsrb#, rtsb#, ctsb#, cdb#, rib#, op2b# uart channel b (same as channel a) a2:a0 d7:d0 csa# (cs#) 16/68# csb# (a3) inta (irq#) intb (logic 0) pwrsave iow# (r/w#) ior# (vcc) reset (reset#) clksel txrdya# txrdyb# rxrdya# rxrdyb#
XR16M2551 2 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 f igure 2. p in o ut a ssignment ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus XR16M2551il32 32-pin qfn -40c to +85c active XR16M2551im48 48-lead tqfp -40c to +85c active 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# csa# csb# pwrsave xtal1 xtal2 iow# cdb# gnd rxrdyb# ior# dsrb# rib# rtsb# ctsb# 16/68# reset dtrb# dtra# rtsa# op2a# rxrdya# inta intb a0 a1 a2 clksel d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# XR16M2551 48-pin tqfp in 16 (intel) mode vcc nc rxrdya# 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 d5 d6 d7 rxb rxa txrdyb# txa txb op2b# cs# a3 pwrsave xtal1 xtal2 r/w# cdb# gnd rxrdyb# nc dsrb# rib# rtsb# ctsb# 16/68# reset# dtrb# dtra# rtsa# op2a# irq# nc a0 a1 a2 clksel d4 d3 d2 d1 d0 txrdya# vcc ria# cda# dsra# ctsa# XR16M2551 48-pin tqfp in 68 (motorola) mode gnd nc 32 31 30 29 1 2 3 4 5 6 7 8 24 23 22 21 20 19 11 12 13 14 15 16 9 10 d5 d6 d7 rxb rxa txa txb csa# csb# xtal1 xtal2 iow# gnd ior# rtsb# ctsb# reset rtsa# inta intb a0 a1 a2 d4 d3 d2 d1 d0 vcc ctsa# XR16M2551 32-pin qfn in 16 (intel) mode 28 27 26 25 18 17 pwrsave 16/68# vcc 32 31 30 29 1 2 3 4 5 6 7 8 24 23 22 21 20 19 11 12 13 14 15 16 9 10 d5 d6 d7 rxb rxa txa txb cs# a3 (csb#) xtal1 xtal2 r/w# gnd vcc (ior#) rtsb# ctsb# reset# (reset) rtsa# irq# nc (intb) a0 a1 a2 d4 d3 d2 d1 d0 vcc ctsa# XR16M2551 32-pin qfn in 68 (motorola) mode 28 27 26 25 18 17 pwrsave 16/68# gnd
XR16M2551 3 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature pin descriptions pin description n ame 32-qfn p in # 48-tqfp p in # t ype d escription data bus interface a2 a1 a0 18 19 20 26 27 28 i address data lines [2:0]. these 3 address lines select one of the internal registers in uart channel a/b during a data bus transaction. d7 d6 d5 d4 d3 d2 d1 d0 2 1 32 31 30 29 28 27 3 2 1 48 47 46 45 44 i/o data bus lines [7:0] (bidirectional). ior# (vcc) 14 19 i when 16/68# pin is high, the intel bus interface is selected and this input becomes read strobe (active low). the fal ling edge instigates an internal read cycle and retrieves the data byte from an inter nal register pointed by the address lines [a2:a0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. when 16/68# pin is low, the motorola bus interface is selected and this input is not used and should be connected to vcc. iow# (r/w#) 12 15 i when 16/68# pin is high, it selects intel bus interface and this input becomes write strobe (active low). the falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. when 16/68# pin is low, the motorola bu s interface is selected and this input becomes read (high) and write (low) signal. csa# (cs#) 7 10 i when 16/68# pin is high, this input is chip select a (active low) to enable channel a in the device. when 16/68# pin is low, this input becomes the chip select (active low) for the motorola bus interface. csb# (a3) 8 11 i when 16/68# pin is high, this input is chip select b (active low) to enable channel b in the device. when 16/68# pin is low, this input becomes address line a3 which is used for channel selection in the motorola bus interface. input low selects channel a and high selects channel b. inta (irq#) 22 30 o when 16/68# pin is high for intel bus interface, this output becomes channel a interrupt output. the output state is defined by the user through the software set - ting of mcr[3]. inta is set to the acti ve mode and op2a# output to low when mcr[3] is set to high. inta is set to the three state mode and op2a# to high when mcr[3] is set to low. see mcr[3]. when 16/68# pin is low for motorola bus in terface, this output becomes device interrupt output (active low, open drain). an external pull-up resistor is required for proper operation.
XR16M2551 4 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 intb 21 29 o uart channel b interrupt output. the output state is defined by the user through the software setting of mcr[3]. intb is set to the active mode and op2b# output low when mcr[3] is set to high. intb is set to the three state mode and op2b# output high when mcr[3] is se t to low (default). see mcr[3]. txrdya# - 43 o uart channel a transmitter ready (active low). the output provides the tx fifo/ thr status for transmit channel a. see table 3 . if it is not used, leave it uncon - nected. rxrdya# - 31 o uart channel a receiver ready (active low). this output provides the rx fifo/ rhr status for receive channel a. see table 3 . if it is not used, leave it uncon - nected. txrdyb# - 6 o uart channel b transmitter ready (active low). the output provides the tx fifo/ thr status for transmit channel b. see table 4 . if it is not used, leave it uncon - nected. rxrdyb# - 18 o uart channel b receiver ready (active low). this output provides the rx fifo/ rhr status for receive channel b. see table 3 . if it is not used, leave it uncon - nected. modem or serial i/o interface txa 5 7 o uart channel a transmit data or infrared encoder data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be high during reset or idle (no data). infrar ed irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is low. if it is not used, leave it unconnected. rxa 4 5 i uart channel a receive data or infrared receive data. normal receive data input must idle high. the infrared receiver pu lses typically idles at low but can be inverted by software control prior going into the decoder, see mcr[6]. if this pin is not used, tie it to vcc or pull it high via a 100k ohm resistor. rtsa# 23 33 o uart channel a request-to-send (active low) or general purpose output. this out - put must be asserted prior to using aut o rts flow control, see efr[6], mcr[1], and ier[6]. ctsa# 25 38 i uart channel a clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7], and ier[7]. this input should be con - nected to vcc when not used. dtra# - 34 o uart channel a data-terminal-ready (activ e low) or general purpose output. if it is not used, leave it unconnected. dsra# - 39 i uart channel a data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cda# - 40 i uart channel a carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. ria# - 41 i uart channel a ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. pin description n ame 32-qfn p in # 48-tqfp p in # t ype d escription
XR16M2551 5 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature op2a# - 32 o output port 2 channel a - the output stat e is defined by the user and through the software setting of mcr[3]. inta is set to the active mode and op2a# output low when mcr[3] is set to high. inta is set to the three state mode and op2a# out - put high when mcr[3] is set to low. see mcr[3]. if inta is used, this output should not be used as a general output el se it will disturb t he inta output function - ality. txb 6 8 o uart channel b transmit data or infrared encoder data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be high during reset or idle (no data). infrar ed irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is low. if it is not used, leave it unconnected. rxb 3 4 i uart channel b receive data or infrared receive data. normal receive data input must idle high. the infrared receiver pu lses typically idles at low but can be inverted by software control prior going in to the decoder, see m cr[6]. if this pin is not used, tie it to vcc or pull it high via a 100k ohm resistor. rtsb# 15 22 o uart channel b request-to-send (active low) or general purpose output. this port must be asserted prior to using auto rt s flow control, see efr[6], m cr[1], and ier[6]. ctsb# 16 23 i uart channel b clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7], and ier[7]. this input should be con - nected to vcc when not used. dtrb# - 35 o uart channel b data-terminal-ready (a ctive low) or general purpose output. if it is not used, leave it unconnected. dsrb# - 20 i uart channel b data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cdb# - 16 i uart channel b carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. rib# - 21 i uart channel b ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. op2b# - 9 o output port 2 channel b - the output stat e is defined by the user and through the software setting of mcr[3]. intb is set to the active mode and op2b# output low when mcr[3] is set to high. intb is set to the three state mode and op2b# out - put high when mcr[3] is set to low. see mcr[3]. if intb is used, this output should not be used as a general output el se it will disturb the intb output function - ality. ancillary signals xtal1 10 13 i crystal or external clock input. xtal2 11 14 o crystal or buffered clock output. pwrsave 9 12 i powersave (active high). this feature isol ates the m2551?s data bus interface from the host preventing other bus activities that cause higher power drain during sleep mode. see sleep mode with auto wake- up and powersave feature section for details. pin description n ame 32-qfn p in # 48-tqfp p in # t ype d escription
XR16M2551 6 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 pin type: i=input, o=output, i/o= input/output, od=output open drain. 16/68# 17 24 i intel or motorola bus select. when 16/68# pin is high, 16 or intel mode, the device will operate in the intel bus type of interface. when 16/68# pin is low, 68 or motorola mode, the device will operate in the motorola bus type of interface. clksel - 25 i baud-rate-generator in put clock prescaler select for channel a and b. this input is only sampled during power up or a reset. connect to vcc for divide by 1 and gnd for divide by 4. mcr[7] can override the state of this pin following a reset or initialization. see mcr bit-7 and figure 5 in the baud rate generator section. reset (reset#) 24 36 i when 16/68# pin is high for intel bus interface, this input becomes reset (active high). when 16/68# pin is low for motoro la bus interface, this input becomes reset# (active low). a 40 ns minimum active pulse on this pin will reset the internal registers and all out - puts of channel a and b. the uart transmitter output will be held high, the receiver input will be ignored and outputs are reset during reset period (see table 16 ). vcc 26 42 pwr 1.62v to 3.63v power supply. gnd 13 17 pwr power supply common, ground. gnd center pad n/a pwr the center pad on the backside of the 32 -qfn package is metallic and should be connected to gnd on the pcb. the thermal pad size on the pcb should be the approximate size of this center pad and should be solder mask defined. the solder mask opening should be at least 0.0025" in wards from the edge of the pcb ther - mal pad. nc - 37 - no connection. pin description n ame 32-qfn p in # 48-tqfp p in # t ype d escription
XR16M2551 7 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 1.0 product description the XR16M2551 (m2551) integrates the functions of 2 enhanced 16c550 universal asynchronous receiver and transmitter (uart). its features set is compatible to the xr16m2550 and xr16v2550 devices but offers intel or motorola data bus interface and powersave to isolate the data bus interface during sleep mode. hence, the m2551 adds 3 more inputs: 16/68#, pwrsave and clksel pins. each uart is independently controlled by its own set of device configuration regi sters. the configuration registers set is 16550 uart compatible for control status and data transfer. addi tionally, each uart chan nel has automatic rts/cts hardware flow control, automatic xon/xoff and special character software flow control, infrared encoder and decoder (irda ver 1.0), and programmable fractional baud ra te generator with a prescaler of divide by 1 or 4. the XR16M2551 can operate from 1.62v to 3.63v. the m2551 is fabricated with an advanced cmos process. enhanced features the m2551 duart provides a solution that supports 16 bytes of transmit and receive fifo memory. the m2551 is designed to work with low su pply voltage and high performance data communication systems, that require fast data processing time. in addition, the se lectable fifo trigger leve l interrupt and automatic hardware/software flow control is uniquely provided fo r good data throughput performance especially when operating in a multi-channel system. data bus interface, intel or motorola type the m2551 provides a single host interface for the 2 uarts and supports intel or motorola microprocessor (cpu) data bus interface. the intel bus compatible interf ace allows direct interconnect to intel compatible type of cpus using ior#, iow# and csa# or csb# inputs for data bus operation. the motorola bus compatible interface instead uses the r/w#, cs# and a3 signals for data bus transactions. few data bus interface signals change their functions depending on user?s selection, see pin description for details. the intel and motorola bus interface selection is made through the 16/68# pin. data rate the m2551 is capable of operation up to 4 mbps at 3.3v with 16x internal sampling clock rate, 8 mbps at 3.3v with 8x sampling clock rate and 16 mbps at 3.3v with 4x sampling clock rate. the device can operate with an external 24 mhz crystal on pins xtal1 and xtal2, or external clock source of up to 64 mhz on xtal1 pin. with a typical crystal of 14.7456 mhz and through a software option, the user can set the prescaler bit for data rates of up to 3.68 mbps. the rich feature set of the m2551 is available through th e internal registers. automatic hardware/software flow control, selectable transmit and receive fifo trigger levels, programmable tx and rx baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
XR16M2551 8 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the m2551 data interface supports the in tel compatible types of cp us and it is compatible to the industry standard 16c550 uart. no clock (oscillato r nor external clock) is required to operate a data bus transaction. each bus cycle is as ynchronous using csa#/csb#, ior# and iow# or cs#, r/w# and a3 inputs. both uart channels share the same data bus fo r host operations. a typical data bus interconnection for intel and motorola mode is shown in figure 3 . 2.2 device reset the reset input resets the internal registers and the seri al interface outputs in both channels to their default state (see table 16 ). an active high pulse of l onger than 40 ns duration will be required to activate the reset function in the device. f igure 3. XR16M2551 t ypical i ntel /m otorola d ata b us i nterconnections vcc vcc op2a# dsra# ctsa# rtsa# dtra# rxa txa ria# cda# op2b# dsrb# ctsb# rtsb# dtrb# rxb txb rib# cdb# gnd a0 a1 a2 uart_csa# uart_csb# ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_intb uart_inta intb inta rxrdya# txrdya# rxrdya# txrdya# rxrdyb# txrdyb# rxrdyb# txrdyb# uart_reset reset serial interface of rs-232, rs-422 serial interface of rs-232, rs-422 (no connect) (no connect) 1.62 to 3.63 volt vcc vcc op2a# dsra# ctsa# rtsa# dtra# rxa txa ria# cda# op2b# dsrb# ctsb# rtsb# dtrb# rxb txb rib# cdb# gnd a0 a1 a2 uart_cs# a3 r/w# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_irq# intb inta rxrdya# txrdya# rxrdya# txrdya# rxrdyb# txrdyb# rxrdyb# txrdyb# reset# vcc uart_reset# (no connect) (no connect) (no connect) vcc intel data bus interconnections motorola data bus interconnections serial interface of rs-232, rs-422 serial interface of rs-232, rs-422
XR16M2551 9 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 2.3 device identification and revision the XR16M2551 provides a device identification code and a device revision code to distinguish the part from other devices and revisions. to read the identification code from the part, it is required to set the baud rate generator regist ers dll and dlm both to 0x00 (dld = 0xxx ). now reading the co ntent of the dvid will provide 0x02 for the XR16M2551 and reading the content of drev will prov ide the revision of the part; for example, a reading of 0x01 means revision a. 2.4 channel a and b selection the uart provides the user with the capability to bi-directionally tr ansfer information be tween an external cpu and an external serial communication device. during intel bus mode (16/68# pin connected to vcc), a low on chip select pins, csa# or csb#, allows the user to select uart channel a or b to configure, send transmit data and/or unload receive data to/from the ua rt. selecting both uarts can be useful during power up initialization to write to the same internal registers, but do not attempt to read from both uarts simultaneously. individual channel select functions are shown in table 1 . during motorola bus mode (16/68# pin connected to gnd), the package interface pins are configured for connection with motorola, and other popular microproce ssor bus types. in this mode the m2551 decodes an additional address, a3, to select one of the uart ports. the a3 address decode function is used only when in the motorola bus mode. see table 2 . 2.5 channel a and b internal registers each uart channel in the m2551 has a set of enhanced registers for control, monitoring and data loading and unloading. the configuration register set is compatib le to those already available in the standard single 16c550 and dual st16c2550. these r egisters function as data holding regi sters (thr/rhr), interrupt status and control registers (isr/ier), a fi fo control register (fcr), receive lin e status and control registers (lsr/ lcr), modem status and control regist ers (msr/mcr), programmable data rate (clock) divisor registers (dll/ dlm/dld), and a user accessible scratchpad register (spr). beyond the general 16c2550 features and capabilities, the m2551 offers enhanced feature registers (efr, xon/xoff 1, xon/xoff 2) that provide automatic rts and cts hardware flow control, and xon/xoff software flow control. all the register functions are discussed in full detail later in ?section 3.0, uart internal registers? on page 23 . t able 1: c hannel a and b s elect in 16 m ode csa# csb# f unction 1 1 uart de-selected 0 1 channel a selected 1 0 channel b selected 0 0 channel a and b selected t able 2: c hannel a and b s elect in 68 m ode cs# a3 f unction 1 n/a uart de-selected 0 0 channel a selected 0 1 channel b selected
XR16M2551 10 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 2.6 dma mode the device does not support direct me mory access. the dma mode (a legacy term) in this document doesn?t mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# a/b and txrdy# a/b output pins. the transmit and receive fifo trigger levels provide additional flexibility to the user for block mode operation. the lsr bits 5- 6 provide an indication when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the m2551 is placed in sing le-character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by th e selected trigger level. in this mode, the m2551 sets the txrdy# pin when the transmit fifo becomes full, and sets the rxrdy# pin when the receive fifo becomes empty. the following table shows their behavior. also see figures 19 through 24 . 2.7 inta and intb outputs the inta and intb interrupt output changes according to the operating mode and enhanced features setup. table 4 and 5 summarize the operating behavior for the transmitter and receiver. also see figures 19 through 24 . t able 3: txrdy# and rxrdy# o utputs in fifo and dma m ode p ins fcr bit -0 = 0 (fifo d isabled ) fcr bit -0 = 1 (fifo e nabled ) fcr bit -3 = 0 (dma m ode d isabled ) fcr bit -3 = 1 (dma m ode e nabled ) rxrdy# a/b low = 1 byte high = no data low = at least 1 byte in fifo high = fifo empty high to low transition when fifo reaches the trigger level, or time-out occurs low to high transition when fifo empties txrdy# a/b low = thr empty high = byte in thr low = fifo empty high = at least 1 byte in fifo low = fifo has at least 1 empty location high = fifo is full t able 4: inta and intb p ins o peration for t ransmitter fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin low = a byte in thr high = thr empty low = fifo above trigger level high = fifo below trigger level or fifo empty t able 5: inta and intb p in o peration f or r eceiver fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) inta/b pin low = no data high = 1 byte low = fifo below trigger level high = fifo above trigger level
XR16M2551 11 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 2.8 crystal oscillator or external clock input the m2551 includes an on-chip oscillator (xtal1 and xtal2) to pro duce a clock for both ua rt sections in the device. the cpu data bus does not r equire this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal 2 pin being the output. fo r programming details, see ? ?section 2.9, programmable baud rate ge nerator with fractional divisor? on page 11 .? f igure 4. t ypical c rystal connections the on-chip oscillator is designed to use an industry stand ard microprocessor cryst al (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 4 ). the programmable baud rate generator is capable of operating with a crystal osc illator frequency of up to 24 mhz. however, with an external clock input on xtal1 pin, it can extend its oper ation up to 64 mhz (16 mbps serial data rate) at 3.3v with an 4x sampling rate. for further reading on the oscillator circuit plea se see the applicat ion note dan108 on the exar web site at http://www.exar.com. 2.9 programmable baud rate generator with fractional divisor each uart has its own baud rate generator (brg) with a prescaler for the transmitter and receiver. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the outpu t of the prescaler clocks to the brg. the brg further divides this clock by a programmable divisor between 1 an d (216 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16x or 8x or 4x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll, dlm and dld registers) defaults to the value of ?1? (dll = 0x01, dlm = 0x00 and dld = 0x00) upon reset. therefore, the brg must be programmed during initialization to the operating data rate. the dll and dlm registers provide the integer part of the divisor and the dld register provides the fractional part of the divisior. only the four lower bits of the dld are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). programming the baud rate g enerator registers dll, dlm and dld provides the capability for selecting the operating data rate. table 6 shows the standard data rates available with a 24mhz crystal or external clock at 16x clock rate. if th e pre-scaler is used (mcr bit-7 = 1), the output data rate will be 4 times less than that shown in table 6 . at 8x sampling rate, these data rates would double and at 4x sampling rate, they would quadruple. also, when using 8x or 4x samplin g mode, please note that th e bit-time will have a jitter c1 22-47pf c2 22-47pf y1 1.8432 mhz to 24 mhz r1 0-120 (optional) r2 500k - 1m xtal1 xtal2
XR16M2551 12 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 (+/- 1/16) whenever the dld is non-zero and is an odd number. when using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s): the closest divisor that is obtainable in the m 2551 can be calculated using the following formula: in the formulas above, please note that: trunc (n) = integer part of n. for example, trunc (5.6) = 5. round (n) = n rounded towards the cl osest integer. for example, roun d (7.3) = 7 and round (9.9) = 10. a >> b indicates right shifting the value ?a? by ?b? number of bits. for example, 0x78a3 >> 8 = 0x0078. required divisor (decimal)=(xtal1 clock frequency / pre scaler) /(serial data rate x 16), with 16x mode, dld[5:4]=?00? required divisor (decimal)= (xtal1 clock frequency / prescaler / (serial data rate x 8), with 8x mode, dld[5:4] = ?01? required divisor (decimal)= (xtal1 clock frequency / prescaler / (serial data rate x 4), with 4x mode, dld[5:4] = ?10? round( (required divisor - trunc(required divisor ) )*16)/16 + trunc( required divisor), where dlm = trunc(required divisor) >> 8 dll = trunc(required divisor) & 0xff dld = round( (required divisor -trunc(required divisor) )*16) f igure 5. b aud r ate g enerator xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll, dlm and dld registers prescaler divide by 1 prescaler divide by 4 16x or 8x or 4x sampling rate clock to transmitter and receiver to other channel fractional baud rate generator logic
XR16M2551 13 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 2.10 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 16 bytes of fifo which includes a byte-wide transmit holding register (thr) . tsr shifts out every data bit with the 16x/8x/4x internal clock. a bit time is 16/8/4 clock periods (see dld[5:4]). the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit (s). the status of the fifo and tsr are reported in the line stat us register (lsr bit-5 and bit-6). t able 6: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling required output data rate d ivisor for 16x clock (decimal) d ivisor o btainable in m2551 dlm p rogram v alue (hex) dll p rogram v alue (hex) dld p rogram v alue (hex) d ata e rror r ate (%) 400 3750 3750 e a6 0 0 2400 625 625 2 71 0 0 4800 312.5 312 8/16 1 38 8 0 9600 156.25 156 4/16 0 9c 4 0 10000 150 150 0 96 0 0 19200 78.125 78 2/16 0 4e 2 0 25000 60 60 0 3c 0 0 28800 52.0833 52 1/16 0 34 1 0.04 38400 39.0625 39 1/16 0 27 1 0 50000 30 30 0 1e 0 0 57600 26.0417 26 1/16 0 1a 1 0.08 75000 20 20 0 14 0 0 100000 15 15 0 f 0 0 115200 13.0208 13 0 d 0 0.16 153600 9.7656 9 12/16 0 9 c 0.16 200000 7.5 7 8/16 0 7 8 0 225000 6.6667 6 11/16 0 6 b 0.31 230400 6.5104 6 8/16 0 6 8 0.16 250000 6 6 0 6 0 0 300000 5 5 0 5 0 0 400000 3.75 3 12/16 0 3 c 0 460800 3.2552 3 4/16 0 3 4 0.16 500000 3 3 0 3 0 0 750000 2 2 0 2 0 0 921600 1.6276 1 10/16 0 1 a 0.16 1000000 1.5 1 8/16 0 1 8 0
XR16M2551 14 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 2.10.1 transmit holding re gister (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 16 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.10.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a tr ansmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes co mpletely empty. see figure 6 below. 2.10.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 16 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its selected trigge r level. the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty (see figure 7 below). f igure 6. t ransmitter o peration in non -fifo m ode f igure 7. t ransmitter o peration in fifo and f low c ontrol m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x or 4x clock ( dld[5:4] ) transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x or 8x or 4x clock ( dld[5:4] ) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.) txfifo1
XR16M2551 15 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 2.11 receiver the receiver section contains an 8-bit receive shift register (rsr) and 16 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x/8x/4x clock (dld[5:4]) for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x/8x/4x clock rate. after 8 clocks (or 4 if 8x or 2 if 4x) the start bit pe riod should be at the center of the start bit. at this time the start bit is sampled and if it is still low it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if th ere were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the rece ive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay unti l it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data read y time-out interrupt when data is not received for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. see figure 8 and figure 9 below. 2.11.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 16 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 8. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x or 8x or 4x clock ( dld[5:4] ) receive data characters data bit validation error tags in lsr bits 4:2
XR16M2551 16 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 2.12 auto rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 10 ): ? enable auto rts flow control using efr bit-6. ? the auto rts function must be started by asserting rts# output pin (mcr bit-1 to high after it is enabled). if using the auto rts interrupt: ? enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin makes a transition from low to high: isr bit-5 will be set to high. f igure 9. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x or 8x or 4x clock ( dld[5:4] ) error tags (16-sets) error tags in lsr bits 4:2 receive data characters fifo trigger=8 example : - rx fifo trigger level selected at 8 bytes (see note below) data fills to 14 data falls to 4 data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1. 16 bytes by 11-bit wide fifo
XR16M2551 17 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 2.13 auto rts hysteresis the m2551 has a new feat ure that provides flow cont rol trigger hysteresis while maintaining co mpatibility with the xr16c850, st16c650a and st16c550 family of uarts. with the auto rts functi on enabled, an interrupt is generated when the receive fifo reaches the selected rx tri gger level. the rts# pin will not be forced high (rts off) until the receive fifo reaches one level above the selected rx trigger level in the trigger table ( table 12 ). the rts# pin will return low af ter the rx fifo is unloaded to one level below the selected rx trigger level in the trigger table ( table 12 ). under the above described conditions, the m2551 will continue to accept data until the receive fifo gets full. the auto rt s function is initiated when the rts# output pin is asserted low (rts on). 2.14 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 10 ): ? enable auto cts flow control using efr bit-7. if using the auto cts interrupt: ? enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (high): is r bit-5 will be set to 1, and uart will suspend transmission as soon as the stop bit of the character in process is shifted ou t. transmission is resumed after the cts# input is re- asserted (low), indicating more data may be sent. t able 7: a uto rts (h ardware ) f low c ontrol r x t rigger l evel int p in a ctivation rts# d e - asserted (h igh ) (c haracters in r x f ifo ) rts# a sserted (l ow ) (c haracters in r x f ifo ) 1 1 4 0 4 4 8 1 8 8 14 4 14 14 14 8
XR16M2551 18 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 f igure 10. a uto rts and cts f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into it s fifo. if interrupt service latency is l ong and data is not being unloaded, uarta monitors its receive data fill level to match the upper th reshold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
XR16M2551 19 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 2.15 auto xon/xoff (software) flow control when software flow control is enabled ( see table 15 ), the m2551 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 character value(s). if receive character(s) (rx) match the programmed values, the m2551 will halt tr ansmission (tx) as soon as th e current character has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspension due to a match of the xoff character, the m2551 will monitor the receive data stream for a match to the xon-1,2 character. if a match is found, the m2551 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit fl ow control registers to 0x00. following reset the user can write any xon/xoff value desired for software flow cont rol. different conditions can be set to detect xon/xoff characters ( see table 15 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the m2551 compares two consecutive receive c haracters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissi ons accordingly. under the above described flow control mechanisms, flow control characters are not placed (sta cked) in the user accessible rx data buffer or fifo. in the event that the receive buff er is overfilling and fl ow control needs to be executed, the m2551 automatically sends an xoff message via the serial tx output to the remote modem. the m2551 sends the xoff-1,2 characters two-character times (= time tak en to send two characters at the programmed baud rate) after the receive fifo crosses the se lected trigger level. to clear this condition, the m2551 will transmit the programmed xon-1,2 characters as soon as receive fifo is less than one trigger level below the selected trigger level. (see table 8 below). * after the trigger level is reached, an xoff character is se nt after a short span of time (= time required to send 2 characters); for example, after 2.083ms has elap sed for 9600 baud and 10-bit word length setting. 2.16 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the m2551 compares each incoming receive character wit h xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit- 4 will be set to indicate detection of special character. although the internal register table shows xon, xoff registers with ei ght bits of character information, the actual number of bits is dependent on the programmed word length. line co ntrol register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the xon, xoff registers corresponds with the lsb bit for the receive character. t able 8: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 1 1 1* 0 4 4 4* 1 8 8 8* 4 14 14 14* 8
XR16M2551 20 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 2.17 infrared mode the m2551 uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the irda 1.0 standard th at stipulates the infrared encoder sends out a 3/16 of a bit wide high-pulse for each ?0? bit in the transmit data st ream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 11 below. the infrared encoder and decoder are enabled by setting m cr register bit-6 to a ?1?. when the infrared feature is enabled, the transmit data output, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero from a reset and power up, see figure 11 . typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the rx pin. each time it senses a light pulse, it returns a high to the data bit stream. however, this is not true with some infrared modules on the market which indicate a low by a light pulse. so the m2551 has a provision to invert the input polarity to accommodate this . in this case user can enable mcr bit-2 to invert the input signal. 2.18 sleep mode with wake-up indicator and powersave feature the m2551 supports low voltage system designs, hence, a sleep mode with auto wake-up and powersave feature is included to reduce power consumption when the device is not actively used. f igure 11. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
XR16M2551 21 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 2.18.1 sleep mode all of these conditions must be satisf ied for the m2551 to enter sleep mode: no interrupts pending for both channels of the m2551 (isr bit-0 = 1) sleep mode of both channels are enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pins are idling high the m2551 stops its crystal oscillator to conserve power in the sleep mode. user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the m2551 resumes normal operation by any of the following when powersave mode is disabled: a receive data start bit transition (high to low) a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the sleep mode is enabled and the m2551 is awake ned by one of the conditions described above, an interrupt is issued by the m2551 to signal to the cpu that it is awake. the lower nibble of the interrupt source register (isr) will read a value of 0x1 for this in terrupt and reading the is r clears this interrupt. since the same value (0x1) is also used to indicate no pending inte rrupt, users should exercise caution while using the sleep mode. the m2551 will return to the sleep mode automatically after all in terrupting conditions have been serviced and cleared. if the m2551 is awakened by the modem inputs, a read to the msr is required to reset the modem inputs. in any case, the sl eep mode will not be ente red while an interrupt is pending from channel a or b. the m2551 will stay in the sleep mode of oper ation until it is disabled by setting ier bit-4 to low. a word of caution: owing to the star ting up delay of the crystal oscillato r after waking up from sleep mode, the first few receive characters may be lost. the number of ch aracters lost during the restart also depends on your operating data rate. more characters are lost when operati ng at higher data rate. also, it is important to keep rx a/b inputs idling high or ?mar king? condition during sleep mode to avoid receiving a ?break? condition upon the restart. this may occur when the external inte rface transceivers (rs-232, rs-422 or another type) are also put to sleep mode and cannot maintain the ?mar king? condition. to avoid this, the designer can use a 47k-100k ohm pull-up resistor on the rxa and rxb pins. 2.18.2 powersave feature if the address lines, data bus lines, iow#, ior#, csa#, csb#, and modem input lines remain steady when the m2551 is in sleep mode, the maximum current will be in the microamp range as specified in the dc electrical characteristics on page 38 . if the input lines are floating or are toggling while the m2551 is in sleep mode, the current can be up to 100 times more. if not using the po wersave feature, then an external buffer would be required to keep the address and data bus lines from to ggling or floating to achieve the low current. but if the powersave feature is en abled (pin 12 connecte d to vcc), this will eliminate the need for an external buffer by internally isolating the address, data and control signals (see figure 1 on page 1 ) from other bus activities that could cause wasteful power drain. the m2551 enters powersave mode when the pwrsave pin is connected to vcc and the m2551 is in sleep m ode (see sleep mode section above). since powersave mode isolates the address, data and control signals, the device will wake-up by: a receive data start bit transition (high to low) a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# the m2551 will return to the powersav e mode automatically after a read to the msr (to reset the modem inputs) and all inte rrupting conditions have been serviced and cl eared. the m2551 will st ay in the powersave mode of operation until it is disabled by setting ier bit-4 to low and/or the pwrsave pin is connected to gnd.
XR16M2551 22 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 2.19 internal loopback the m2551 uart provides an inter nal loopback capability for system diagnostic purposes. the internal loopback mode is enabled by setting mcr register bit-4 to hi gh. all regular uart functions operate normally. figure 12 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx, rts# and dtr# pins are held while the cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input pin must be held high during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. also , auto rts/cts flow control is not supported during internal loopback. f igure 12. i nternal l oop b ack in c hannel a and b txa/txb rxa/rxb modem / general purpose control logic internal data bus lines and control signals rtsa#/rtsb# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) ctsa#/ctsb# dtra#/dtrb# dsra#/dsrb# ria#/rib# cda#/cdb# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc vcc op2a#/op2b#
XR16M2551 23 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 3.0 uart internal registers each of the uart channel in the m2551 has its own se t of configuration registers selected by address lines a0, a1 and a2 with csa# or csb# selecting the channel. the complete register set is shown on table 9 and table 10 . t able 9: uart channel a and b uart internal registers a ddresses a2 a1 a0 r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - divisor lsb read/write lcr[7] = 1, lcr 0xbf 0 0 1 dlm - divisor msb read/write 0 1 0 dld - divisor fractional read/write lcr[7] = 1, lcr 0xbf, efr[4] = 1 0 0 0 drev - device revision code read-only dll, dlm = 0x00, lcr[7] = 1, lcr 0xbf 0 0 1 dvid - device identification code read-only 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only lcr 0xbf 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr 0xbf 1 0 1 lsr - line status register read-only 1 1 0 msr - modem status register read-only 1 1 1 spr - scratch pad register read/write e nhanced r egisters 0 1 0 efr - enhanced function register read/write lcr = 0xbf 1 0 0 xon-1 - xon character 1 read/write 1 0 1 xon-2 - xon character 2 read/write 1 1 0 xoff-1 - xoff character 1 read/write 1 1 1 xoff-2 - xoff character 2 read/write
XR16M2551 24 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 t able 10: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts int. enable rts int. enable xoff int. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 lcr 0xbf int source bit-5 int source bit-4 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal lopback enable op2#/int output enable (op1#) rts# output control dtr# output control lcr 0xbf brg pres - caler ir mode enable xonany ir input invert 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx fram - ing error rx parity error rx over - run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 1 0 dld rd/wr 0 0 4x mode 8x mode bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr 0xbf efr[4] = 1 0 0 0 drev rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr 0xbf dll=0x00 dlm=0x00 0 0 1 dvid rd 0 0 0 0 0 0 1 0
XR16M2551 25 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 15. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 13. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive interr upts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the selected trig - ger level. it will be cleared when the fifo drops below the sele cted trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. enhanced registers 0 1 0 efr rd/wr auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5], dld soft- ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 lcr=0xbf 1 0 0 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 10: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
XR16M2551 26 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals high for fifo enable; resettin g ier bits 0-3 enables the XR16M2551 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in th e non-fifo mode or when the receive fifo has reached the selected trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when data in the fifo falls below the selected trigger level in th e fifo mode. if the thr is empty when this bit is enabled , an interrupt will be generated. ? logic 0 = disable transmit ready interrupt (default). ? logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is high, it will generate an interr upt to inform the host controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bits 2-4 generate an in terrupt when the character with errors is read out of the fifo. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) ? logic 0 = disable sleep mode (default). ? logic 1 = enable sleep mode. see sleep mode section for further details. ier[5]: xoff interrupt enable (requires efr bit-4=1) ? logic 0 = disable the software flow cont rol, receive xoff interrupt (default). ? logic 1 = enable the software flow control, receive xo ff interrupt. see software flow control section for details.
XR16M2551 27 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature ier[6]: rts# output interrupt enable (requires efr bit-4=1) ? logic 0 = disable the rts# interrupt (default). ? logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high. ier[7]: cts# input interrupt enable (requires efr bit-4=1) ? logic 0 = disable the cts# interrupt (default). ? logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt level to be se rviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 11 , shows the data values (bit 0-5) for the inte rrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level or tx fifo empty. ? msr is by any of the msr bits 0, 1, 2 and 3. ? receive xoff/special character is by det ection of a xoff or special character. ? cts# is when its transmitter toggles the input pin (f rom low to high) during auto cts flow control. ? rts# is when its receiver toggles the output pin (f rom low to high) during auto rts flow control. ? wake-up indicator is when the uart comes out of sleep mode. 4.4.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register. ? rxrdy interrupt is cleared by reading data until fifo fa lls below the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr. ? txrdy interrupt is cleared by a read to the isr register or writing to thr. ? msr interrupt is cleared by a read to the msr register. ? xoff interrupt is cleared by a read to isr or when xon character(s) is received. ? special character interrupt is cleared by a read to isr or after the next character is received. ? rts# and cts# flow control interrupts are cleared by a read to the msr register. ? wake-up indicator is cleared by a read to the isr register.
XR16M2551 28 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition) or the device has come out of sleep mode. isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels (see interrupt source table 11 ). isr[4]: xoff/xon or special character interrupt status this bit is enabled when efr bit-4 is set to high. isr bi t-4 indicates that the receiver detected a data match of the xoff character(s). if this is an xoff/xon interrupt, it can be cleared by a read to the isr. if it is a special character interr upt, it can be cleared by reading isr or it will automatically clear after the next character is received. isr[5]: rts#/cts# interrupt status this bit is enabled when efr bit-4 is set to high. isr bit-5 indicates that the cts# or rts# has been de- asserted. isr[7:6]: fifo enable status these bits are set to low when the fifos are disabled. they are set to high when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fi fos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to high when other fcr bits are written or they will not be programmed. t able 11: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default) or wake-up indicator
XR16M2551 29 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default) ? logic 1 = reset the receive fifo point ers (the receive shift register is not cleared or alte red). this bit will return to low after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers (the transmit shift register is not clear ed or altered). this bit will return to low after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. ? logic 0 = normal operation (default). ? logic 1 = dma mode. fcr[5:4]: transmit fifo trigger select (requires efr bit-4=1) (logic 0 = default, tx trigger level = 1) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 12 below shows the selections. efr bit-4 must be set to ?1? before these bits can be accessed. wh ichever selection is made last applies to both the rx and tx side. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in the fifo crosses the trigger level. table 12 shows the complete selections. whichever selection is made last ap plies to both the rx and tx side. 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. t able 12: t ransmit and r eceive fifo t rigger t able and l evel s election fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 (default) 4 8 14 1 (default) 4 8 14 16c550, 16c2550, 16c2552, 16c554, 16c580 compatible.
XR16M2551 30 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 13 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to high , lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to high for th e transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bi t is forced to low for th e transmit and receive data. bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2
XR16M2551 31 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space", low state). this condition remains, until disabled by setting lcr bit-6 to low. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space?, low, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll, dlm and dld) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/mod em interface signals or g eneral purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output high (default). ? logic 1 = force dtr# output low. mcr[1]: rts# output the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6. if the modem interface is not used, this output may be used as a general purpose output. ? logic 0 = force rts# high (default). ? logic 1 = force rts# low. mcr[2]: irda rx inversion or op1# (legacy term) when infrared mode is enabled (mcr[6]=1 and efr[4]=1), this bit selects the idle state of the encoded irda data. in internal loopback mode, this bi t functions like the op 1# in the 16c550. ? logic 0 = select rx input as ac tive-low encoded irda data (i dle state will be low) (default). ? logic 1 = select rx input as active-high encoded irda data (idle state will be high). in the internal loopback mode , this bit controls the state of the mode m input ri# bit in the msr register as shown in figure 12 . t able 13: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity to mark, ?1? 1 1 1 forced parity to space, ?0?
XR16M2551 32 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 mcr[3]: op2# output / int output enable this bit enables or disables the operation of int, interr upt output. if int output is not used, op2# can be used as a general purpose output. also, if 16/68# pin selects motorola bus interface mode, this bit must be set to low . ? logic 0 = int (a-b) outputs disabled (three stat e mode) and op2# output set high(default). ? logic 1 = int (a-b) outputs enabled (active mode) and op2# output set low. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 12 . mcr[5]: xon-any enable (requires efr bit-4=1) ? logic 0 = disable xon-any function (default). ? logic 1 = enable xon-any function. in this mode, any rx character re ceived will resume transmit operation. the rx character will be loaded into the rx fifo, unless the rx characte r is an xon or xo ff character and the m2551 is programmed to use the xon/xoff flow control. mcr[6]: infrared encoder/decoder enable (requires efr bit-4=1) ? logic 0 = enable the standard modem receive an d transmit input/output interface (default). ? logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. while in this mode, the infrared tx ou tput will be idling low. see?infrared mode? on page 20. mcr[7]: clock prescaler select (requires efr bit-4=1) ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun error flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error tag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct pa rity information and is suspect. this error is associated with the char acter available for reading in rhr.
XR16M2551 33 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature lsr[3]: receive data framing error tag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break error tag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx wa s low for at least one char acter frame time). in the fifo mode, only one break character is loaded into the fifo. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to high when the last data byte is transferred from the transmit holding register to the tran smit shift register. the bit is reset to low concurrently with the data loading to the transmit holding register by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to high whenever t he transmitter goes idle. it is set to low whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to high whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears wh en there is no more error(s) in any of the bytes in the rx fifo. 4.9 modem status register (msr) - read only this register provides the current state of the modem interf ace input signals. lower four bits of this register are used to indicate the changed information. these bits are set to high whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a low to high, ending of the ringing signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3).
XR16M2551 34 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if ms r interrupt is enab led (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a high on the cts# pin will stop uart transmitte r as soon as the current character has finished transmission, and a low will re sume data transmission. normally ms r bit-4 bit is the complement of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the complement of the dsr# input. in the loopback mode , this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# input. in the loopback mode th is bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the co ntent of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.11 baud rate generator registers (dll, dlm and dld) - read/write these registers make-up the value of the baud rate divi sor. the concatenation of the contents of dlm and dll is a 16-bit value is then added to dld[3:0]/16 to achieve the fractional baud rate divisor. dld must be enabled via efr bit-4 before it can be accessed. see?programmable baud rate generator with fractional divisor? on page 11. dld[5:4]: sampli ng rate select these bits select the data sampling rate. by default, the data sampling rate is 16x. the maximum data rate will double if the 8x mode is selected and will quadruple if th e 4x mode is selected. see table 14 below. dld[7:6]: reserved t able 14: s ampling r ate s elect dld[5] dld[4] s ampling r ate 0 0 16x 0 1 8x 1 x 4x
XR16M2551 35 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 4.12 device identification register (dvid) - read only this register contains the device id (0x02 for xr16m255 1). prior to reading this register, dll and dlm should be set to 0x00 (dld = 0xxx). 4.13 device revision register (drev) - read only this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00 (dld = 0xxx). 4.14 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 15 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to low (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. t able 15: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2 receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control receiver compares xon1 and xon2, xoff1 and xoff2
XR16M2551 36 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4- 7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, and dld to be modified. after modifying any enhanced bits, efr bi t-4 can be set to low to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, high. ? logic 0 = modification disable/latch enhanced features. ie r bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5- 7, and dld are saved to retain the user settings. after a reset, the ier bits 4-7, is r bits 4-5, fcr bits 4-5, mcr bits 5-7, and dld are set to low to be compatible with st16 c550 mode (default). ? logic 1 = enables the above-mentioned regist er bits to be modified by the user. efr[5]: special character detect enable ? logic 0 = special character detect disabled (default). ? logic 1 = special character detect enabled. the ua rt compares each incoming receive character with data in xoff-2 register. if a match exists, the receive data will be transfer red to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xo ff1 (efr [1:0]= ?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= ?01?) then flow control works normally, but xoff2 will not go to the fifo, and will g enerate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to high. wh en auto rts is selected, an interrupt will be generated when the receive fifo is filled to the select ed trigger level and rts de-asserts high at the next upper tr igger level. rts# will return low when fifo data falls below the next lower trigger level. the rts# output must be asse rted (low) before the auto rts can ta ke effect. rts# pin will function as a general purpose output when hardware flow control is disabled. ? logic 0 = automatic rts flow control is disabled (default). ? logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. ? logic 0 = automatic cts flow control is disabled (default). ? logic 1 = enable automatic cts flow control. data tr ansmission stops when cts# input de-asserts high. data transmission resumes when cts# returns low. 4.14.1 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the programmable software fl ow control characters xoff1, xoff2, xon1, and xon2. for more details, see table 8 .
XR16M2551 37 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature t able 16: uart reset conditions for channel a and b registers reset state dlm, dll dlm = 0x00 and dll = 0x01. only resets to these values during a power up. they do not reset when the reset pin is asserted. dld bits 7-0 = 0x00 rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = low bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx high op2# high rts# high dtr# high rxrdy# high txrdy# low int (irq#) three-state condition (16 mode) high (68 mode)
XR16M2551 38 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 test 1: the following inputs must rema in steady at vcc or gnd state to mi nimize sleep current: a0-a2, d0-d7, ior#, iow# (r/w#), csa# (cs#), csb# (a3) and all modem inputs. also, rxa and rxb inputs must idle high while asleep. floating inputs may resu lt in sleep currents in the ma range. 5.0 electrical characteristics absolute maximum ratings power supply range 4 volts voltage at any pin gnd-0.3v to 4v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data ( margin of error: 15% ) thermal resistance (32-qfn) theta-ja =33 o c/w, theta-jc = 22 o c/w thermal resistance (48-tqfp) theta-ja =59 o c/w, theta-jc = 16 o c/w dc electrical characteristics ta = -40 o to +85 o c, vcc is 1.62v to 3.63v s ymbol p arameter l imits 1.8v m in m ax l imits 2.5v m in m ax l imits 3.3v m in m ax u nits c onditions v ilck clock input low level -0.3 0.3 -0.3 0.6 -0.3 0.6 v v ihck clock input high level 1.4 vcc 1.8 vcc 2.4 vcc v v il input low voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 v v ih input high voltage 1.4 vcc 1.8 vcc 2.0 vcc v v ol output low voltage 0.4 0.4 0.4 v v v i ol = 4 ma i ol = 2 ma i ol = 1.5 ma v oh output high voltage 1.4 1.8 2.0 v v v i oh = -1 ma i oh = -400 ua i oh = -200 ua i il input low leakage current 10 10 10 ua i ih input high leakage current 10 10 10 ua c in input pin capacitance 5 5 5 pf i cc power supply current 0.5 1 2 ma xtal1 = 2 mhz i sleep sleep current 5 8 15 ua see test 1
XR16M2551 39 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature for powersave, the uart internally isolates all of these inputs (except the modem inputs) therefore eliminating any unnecessary external buffers to keep the inputs steady. see?powersave feature? on page 21. ac electrical characteristics unless otherwise noted: ta = -40 o to +85 o c, vcc=1.62 - 3.63v, 70 pf load where applicable s ymbol p arameter l imits 1.8v 10% m in m ax l imits 2.5v 10% m in m ax l imits 3.3v 10% m in m ax u nit xtal1 uart crystal oscillator 24 24 24 mhz eclk external clock 32 50 64 mhz t eclk external clock time period 15 10 7 ns t as address setup time (16 mode) 0 0 0 ns t ah address hold time (16 mode) 0 0 0 ns t cs chip select width (16 mode) 65 40 35 ns t rd ior# strobe width (16 mode) 65 40 35 ns t dy read cycle delay (16 mode) 65 40 35 ns t rdv data access time (16 mode) 60 35 30 ns t dd data disable time (16 mode) 25 25 25 ns t wr iow# strobe width (16 mode) 65 40 35 ns t dy write cycle delay (16 mode) 65 40 35 ns t ds data setup time (16 mode) 20 10 10 ns t dh data hold time (16 mode) 3 3 3 ns t ads address setup (68 mode) 0 0 0 ns t adh address hold (68 mode) 0 0 0 ns t rws r/w# setup to cs# (68 mode) 0 0 0 ns t rda read data access (68 mode) 60 35 30 ns t rdh read data disable (68 mode) 25 25 25 ns t wds write data setup (68 mode) 20 10 10 ns t wdh write data hold (68 mode) 3 3 3 ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) 5 5 5 ns t csl cs# width (68 mode) 65 40 35 ns t csd cs# cycle delay (68 mode) 65 40 35 ns t wdo delay from iow# to output 50 50 50 ns t mod delay to set interrupt from modem input 50 50 50 ns t rsi delay to reset interrupt from ior# 50 50 50 ns
XR16M2551 40 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 t ssi delay from stop to set interrupt 1 1 1 bclk t rri delay from ior# to reset interrupt 45 45 45 ns t si delay from stop to interrupt 45 45 45 ns t int delay from initial int reset to transmit start 8 24 8 24 8 24 bclk t wri delay from iow# to reset interrupt 45 45 45 ns t ssr delay from stop to set rxrdy# 1 1 1 bclk t rr delay from ior# to reset rxrdy# 45 45 45 ns t wt delay from iow# to set txrdy# 45 45 45 ns t srt delay from center of start to reset txrdy# 8 8 8 bclk t rst reset pulse width 40 40 40 ns bclk baud clock 16x or 8x or 4x of data rate hz f igure 13. c lock t iming ac electrical characteristics unless otherwise noted: ta = -40 o to +85 o c, vcc=1.62 - 3.63v, 70 pf load where applicable s ymbol p arameter l imits 1.8v 10% m in m ax l imits 2.5v 10% m in m ax l imits 3.3v 10% m in m ax u nit external clock t ech t ecl vih vil t eclk
XR16M2551 41 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature f igure 14. m odem i nput /o utput t iming f or c hannels a & b f igure 15. 16 m ode (i ntel ) d ata b us r ead t iming iow # rts# dtr# cd# cts# dsr# int ior# ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state active active t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# ior# d0-d7 rdtm t cs t rd
XR16M2551 42 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 f igure 16. 16 m ode (i ntel ) d ata b us w rite t iming f igure 17. 68 m ode (m otorola ) d ata b us r ead t iming 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a2 csa#/ csb# iow# d0-d7 t cs t wr 68read t ads t rdh t adh t csl t rda t csd t rws valid address valid address valid data a0-a3 cs# r/w# d0-d7 t rwh valid data
XR16M2551 43 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature f igure 18. 68 m ode (m otorola ) d ata b us w rite t iming f igure 19. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b 68write t ads t adh t csl t wds t csd t rws valid address valid address valid data a0-a3 cs# r/w# d0-d7 t rwh valid data t wdh rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr)
XR16M2551 44 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 f igure 20. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b f igure 21. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) ier[1] enabled rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
XR16M2551 45 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b f igure 23. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when tx fifo fills up to the trigger level.
XR16M2551 46 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b tx txrdy# iow# int* d0:d7 s txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri t (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level at least 1 empty location in fifo t srt tx fifo full t wt t si isr read isr read *int cleared when the isr is read or when tx fifo fills up to trigger level. ier[1] enabled
XR16M2551 47 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature package dimensions (32 pin qfn - 5 x 5 x 0.9 mm) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 d 0.193 0.201 4.90 5.10 d2 0.138 0.150 3.50 3.80 b 0.007 0.012 0.18 0.30 e 0.0197 bsc 0.50 bsc l 0.014 0.018 0.35 0.45 k 0.008 - 0.20 - note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm
XR16M2551 48 high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 package dimensions (48 pin tqfp - 7 x 7 x 1 mm) note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.039 0.047 1.00 1.20 a 1 0.002 0.006 0.05 0.15 a 2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d 1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 36 25 24 13 1 1 12 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c
49 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2007 exar corporation datasheet may 2007. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. XR16M2551 rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature revision history d ate r evision d escription july 2006 p1.0.0 preliminary datasheet. january 2007 1.0.0 final datasheet. updated ac electrical characteristics. may 2007 1.0.1 added "gnd center pad" to pin description. updated 32 pin qfn package dimen - sions drawing to show minimum "k" parameter. may 2007 1.0.2 updated ac electrical characteristics. write data hold time values (t dh and t wdh ) improved from 5ns to 3ns.
XR16M2551 i high performance low voltage duart with 16-byte fifo and powersave feature rev. 1.0.2 table of contents general description ......... ................ ................ ................. .............. .............. .......... 1 a pplications ............................................................................................................................... ................ 1 f eatures ............................................................................................................................... ..................... 1 f igure 1. XR16M2551 b lock d iagram ............................................................................................................................... ......... 1 f igure 2. p in o ut a ssignment ............................................................................................................................... ...................... 2 ordering information ............................................................................................................................... . 2 pin descriptions ............ ................ ................. ................ ................. ................ .......... 3 1.0 product description........................................................................................................ ............... 7 2.0 functional descriptions.................................................................................................... ........... 8 2.1 cpu interface.............................................................................................................. ................................... 8 f igure 3. XR16M2551 t ypical i ntel /m otorola d ata b us i nterconnections .......................................................................... 8 2.2 device reset .... .............. .............. .............. .............. .............. .............. .............. ......... .................................... 8 2.3 device identification and revi sion........... .............. .............. .............. .............. ........... ........... ............... 9 2.4 channel a and b selection......... .............. .............. .............. .............. ............ ........... .......... ..................... 9 t able 1: c hannel a and b s elect in 16 m ode ............................................................................................................................ 9 t able 2: c hannel a and b s elect in 68 m ode ............................................................................................................................ 9 2.5 channel a and b internal register s ............... .............. .............. .............. ........... ........... .......... .......... 9 2.6 dma mode................................................................................................................... ..................................... 10 t able 3: txrdy# and rxrdy# o utputs in fifo and dma m ode ........................................................................................... 10 2.7 inta and intb outputs ........... .............. .............. .............. .............. .............. ........... .......... ......................... 10 t able 4: inta and intb p ins o peration for t ransmitter ...................................................................................................... 10 t able 5: inta and intb p in o peration f or r eceiver ............................................................................................................. 10 2.8 crystal oscillator or external clock input .......... .............. .............. ........... ........... ........... ....... 11 f igure 4. t ypical c rystal connections ............................................................................................................................... .... 11 2.9 programmable baud rate generator with fractional divisor............................................ 11 f igure 5. b aud r ate g enerator ............................................................................................................................... ................ 12 t able 6: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling ................................................... 13 2.10 transmitter ............................................................................................................... ................................. 13 2.10.1 transmit holding register (thr) - write only ............................................................................ ............. 14 2.10.2 transmitter operation in non-fifo mode .................................................................................. ................ 14 f igure 6. t ransmitter o peration in non -fifo m ode .............................................................................................................. 14 2.10.3 transmitter operation in fifo mode ...................................................................................... ..................... 14 f igure 7. t ransmitter o peration in fifo and f low c ontrol m ode ..................................................................................... 14 2.11 receiver .................................................................................................................. ..................................... 15 2.11.1 receive holding register (rhr) - read-only .............................................................................. .............. 15 f igure 8. r eceiver o peration in non -fifo m ode .................................................................................................................... 15 f igure 9. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ......................................................................... 16 2.12 auto rts (hardware) flow control .......................................................................................... ...... 16 2.13 auto rts hysteresis...................................................................................................... ......................... 17 t able 7: a uto rts (h ardware ) f low c ontrol ........................................................................................................................ 17 2.14 auto cts flow control .................................................................................................... .................... 17 f igure 10. a uto rts and cts f low c ontrol o peration ....................................................................................................... 18 2.15 auto xon/xoff (software) flow control..................................................................................... . 19 t able 8: a uto x on /x off (s oftware ) f low c ontrol ............................................................................................................... 19 2.16 special character detect ...... .............. .............. .............. .............. .............. ............ ......... ................. 19 2.17 infrared mode ............................................................................................................. .............................. 20 f igure 11. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 20 2.18 sleep mode with wake-up indicator and powers ave feature..... ........... ........... ........... ....... 20 2.18.1 sleep mode .............................................................................................................. ............................................... 21 2.18.2 powersave feature....................................................................................................... ..................................... 21 2.19 internal loopback ..... .............. .............. .............. .............. ........... ........... ........... .......... ......................... 22 f igure 12. i nternal l oop b ack in c hannel a and b ................................................................................................................ 22 3.0 uart internal registers .................................................................................................... ......... 23 t able 9: uart channel a and b uart internal registers ............................................................................. .......... 23 t able 10: internal registers description. s haded bits are enabled when efr b it -4=1 ....................................... 24 4.0 internal register descriptions............................................................................................. .. 25 4.1 receive holding register (rhr) - read- only ........... .............. .............. .............. .............. ............. .. 25 4.2 transmit holding register (thr) - write-only ............................................................................... 25 4.3 interrupt enable register (ier) - read/write.......... .............. .............. .............. .............. ............. .. 25
XR16M2551 ii rev. 1.0.2 high performance low voltage duart with 16-byte fifo and powersave feature 4.3.1 ier versus receive fifo interrupt mode operation ......................................................................... ...... 25 4.3.2 ier versus receive/transmit fifo polled mode operation.................................................................. 26 4.4 interrupt status register (isr) - read-only ......... .............. .............. .............. ............... .............. .. 27 4.4.1 interrupt generation: .................................................................................................... .................................... 27 4.4.2 interrupt clearing: ...................................................................................................... ....................................... 27 t able 11: i nterrupt s ource and p riority l evel ..................................................................................................................... 28 4.5 fifo control register (fcr) - write-only ................................................................................... ..... 28 t able 12: t ransmit and r eceive fifo t rigger t able and l evel s election .......................................................................... 29 4.6 line control register (lcr) - read/write ................................................................................... ..... 29 t able 13: p arity selection .............................................................................................................................. .......................... 31 4.7 modem control register (m cr) or general purpose outp uts control - read/write . 31 4.8 line status register (lsr) - read only..................................................................................... ......... 32 4.9 modem status register (msr) - read only .................................................................................... ... 33 4.10 scratch pad register (spr) - re ad/write .............. .............. .............. .............. ............... ............ .... 34 4.11 baud rate generator registers (dll, dlm and dld) - read/write ...... .............. .............. ..... 34 t able 14: s ampling r ate s elect .............................................................................................................................. ................. 34 4.12 device identification register (d vid) - read only....................................................................... 3 5 4.13 device revision register (drev) - read only... ............................................................................ .. 35 4.14 enhanced feature register (efr) .............. .............. .............. .............. .............. ............ ......... .......... 35 t able 15: s oftware f low c ontrol f unctions ........................................................................................................................ 35 4.14.1 software flow control registers (xof f1, xoff2, xon1, xon2) - read/write .............................. 36 t able 16: uart reset conditions for channel a and b ................................................................................ ............ 37 5.0 electrical characteristics ................................................................................................. .... 38 a bsolute m aximum r atings .................................................................................................................... 38 t ypical package thermal resistance data (m argin of error : 15%) ............................................... 38 dc e lectrical c haracteristics ............................................................................................................. 38 ac e lectrical c haracteristics ............................................................................................................. 39 f igure 13. c lock t iming ............................................................................................................................... .............................. 40 f igure 14. m odem i nput /o utput t iming f or c hannels a & b ................................................................................................. 41 f igure 15. 16 m ode (i ntel ) d ata b us r ead t iming ................................................................................................................... 41 f igure 16. 16 m ode (i ntel ) d ata b us w rite t iming ................................................................................................................. 42 f igure 17. 68 m ode (m otorola ) d ata b us r ead t iming .......................................................................................................... 42 f igure 18. 68 m ode (m otorola ) d ata b us w rite t iming ......................................................................................................... 43 f igure 19. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ......................................................... 43 f igure 20. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a & b ....................................................... 44 f igure 21. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a & b........................................ 44 f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a & b......................................... 45 f igure 23. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a & b ........................... 45 f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a & b ............................ 46 p ackage d imensions (32 pin qfn - 5 x 5 x 0.9 mm ) ............................................................................... 47 p ackage d imensions (48 pin tqfp - 7 x 7 x 1 mm ) .................................................................................. 48 r evision h istory ............................................................................................................................... ...... 49 table of contents .......... ................ ................. ................ .............. .............. .............. i

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